With reference to FIG. 1, a typical metal oxide semiconductor field effect transistor (MOSFET) 10 is illustrated. The MOSFET 10 is formed by creating a source region 12 and a drain region 14 in a semiconductor wafer 16 and placing a gate electrode 18 over the surface of the semiconductor wafer 16 between the source region 12 and the drain region 14. The source region 12 and the drain region 14 are heavily doped with N-type material. The gate electrode 18 is isolated from the surface of the semiconductor wafer 16 by an appropriate gate dielectric layer 20. In the illustrated embodiment, a lightly doped drain region 22 in the semiconductor wafer 16 extends from the drain region 14 to the gate electrode 18. Also, a body region 24 may be formed in the semiconductor wafer 16 adjacent to the source region 12 wherein the source region 12 is between the body region 24 and the gate electrode 18.
Electrical contacts to the body region 24, source region 12, and drain region 14 may be established through conductive vias. As illustrated, a body contact via 26 and a source contact via 28 extend from the respective body region 24 and source region 12 to a source contact 30. A drain contact via 32 extends from the drain region 14 to a drain contact 34. The electrical contact to the gate electrode 18 is not shown.
MOSFETs 10 are used in numerous electrical applications, including those that are required to operate at high frequencies and over wide operating voltage ranges. Designers are constantly faced with the challenge of creating MOSFETs 10 that operate at higher frequencies and higher operating voltage ranges. The inherent drain-to-gate capacitance of the MOSFET 10 is a significant obstacle in achieving higher operating frequencies. The breakdown voltage of the MOSFET 10 is a significant obstacle in achieving wider operating voltage ranges.
Reference is now made to FIG. 2. In an effort to reduce drain-to-gate capacitance and increase breakdown voltage, a shield 36 was formed over the gate electrode 18 and lightly doped drain region 22. The shield 36 effectively reduces drain-to-gate capacitance. FIGS. 1 and 2 provide electrostatic potential contour lines throughout the semiconductor wafer 16 at the breakdown voltage of the respective MOSFET 10. As illustrated, the breakdown voltage is significantly increased when the shield 36 is employed.
The shield 36 is isolated from the gate electrode 18 and the surface of the semiconductor wafer 16 by extending a gate electrode spacer 38 from the gate electrode 18 toward the drain region 14. Notably, the shield 36 is formed by depositing an additional polysilicon layer over the extended gate electrode spacer 38. Unfortunately, formation of the additional polysilicon layer requires an additional polysilicon process step, which is not part of a common MOSFET manufacturing process. Further, the widely varying topology of the MOSFET 10 makes the etching process for creating the shield 36 from the additional polysilicon layer complex.
Accordingly, there is a need to create a shield that reduces drain-to-gate capacitance and increases breakdown voltage of a MOSFET 10 in a more efficient and effective manner. In particular, there is a need to create a shield that does not require adding an additional polysilicon layer to the normal manufacturing process or require etching over a complex topology.